minor lora changes

This commit is contained in:
2020-07-15 22:35:46 +02:00
parent a2c3b40435
commit 9c94faa24d

View File

@@ -347,8 +347,6 @@ public:
/** send the given data */
int send(const uint8_t* data, uint8_t len, bool async) {
debugMod2(NAME, "tx(%d bytes, async:%d)", len, async);
//if (len > MAX_PKT_LENGTH) {return -1;}
if (isTransmitting()) {return 0;}
@@ -366,12 +364,13 @@ public:
for (uint16_t i = 0; i < len; ++i) {writeRegister(REG_FIFO, data[i]);}
writeRegister(REG_PAYLOAD_LENGTH, len);
//if ((async) && (_onTxDone)) writeRegister(REG_DIO_MAPPING_1, 0x40); // DIO0 => TXDONE
// put in TX mode
//debugMod(NAME, "starting TX");
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
debugMod2(NAME, "tx(%d bytes, async:%d)", len, async);
if (!async) {
//debugMod(NAME, "waiting");
@@ -391,11 +390,13 @@ public:
/** switch to RX mode, but only for a single packet */
void rxSingle() {
debugMod(NAME, "rxSingle()");
enableRX(true);
}
/** switch to RX mode, continuously */
void rxContinuous() {
debugMod(NAME, "rxContinuous()");
enableRX(false);
}
@@ -456,7 +457,7 @@ public:
private:
void yield() {
usleep(10*1000); // 10 ms. this is the minimum when running with 100 Ticks FreeRTOS
//usleep(10*1000); // 10 ms. this is the minimum when running with 100 Ticks FreeRTOS
}
/**
@@ -478,9 +479,7 @@ private:
/** switch to RX-mode. either for a single frame or permanent */
void enableRX(bool single) {
debugMod1(NAME, "rx(single: %d)", single);
// reset FIFO address
writeRegister(REG_FIFO_ADDR_PTR, 0);