214 lines
6.9 KiB
C++
214 lines
6.9 KiB
C++
// https://github.com/Jean-MarcHarvengt/VGA_t4
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// https://forum.pjrc.com/threads/63243-Writing-Directly-to-SGTL5000-CODEC-DACs
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// https://community.nxp.com/t5/Kinetis-Microcontrollers/is-there-any-demo-code-for-using-I2S/m-p/196195/highlight/true
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// https://github.com/PaulStoffregen/Audio/blob/99b9472afd24bea13efc799742c0ea432ef2303a/output_i2s.cpp
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#include "../base.h"
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#define USE_DMA
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#ifdef USE_DMA
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#include <DMAChannel.h>
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static DMAChannel dma;
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#endif
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#define SAMPLES_PER_BUFFER 1024
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#define NUM_BUFFERS 4
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static DMAMEM __attribute__((aligned(32))) int16_t audioBuffer[SAMPLES_PER_BUFFER*NUM_BUFFERS];
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static volatile uint8_t freeBuffers = NUM_BUFFERS;
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static volatile uint8_t curBuffer = 0;
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template <int CHANNELS, int SAMPLE_RATE_HZ> class I2S {
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static constexpr const char* NAME = "I2S";
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public:
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I2S() {
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log_d(NAME, "ctor()");
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//config_sai1();
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}
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void start() {
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log_d(NAME, "start()");
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// clear
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//arm_dcache_flush_delete(txBuffer, txBufferSize); // ??
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config_sai1();
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#ifdef USE_DMA
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dma.begin(true); // Allocate the DMA channel first
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dma.TCD->SADDR = audioBuffer; //source address
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dma.TCD->SOFF = 2; // source buffer address increment per transfer in bytes
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); // specifies 16 bit source and destination
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dma.TCD->NBYTES_MLNO = 2; // bytes to transfer for each service request///////////////////////////////////////////////////////////////////
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dma.TCD->SLAST = -sizeof(audioBuffer); // last source address adjustment
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dma.TCD->DOFF = 0; // increments at destination
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dma.TCD->CITER_ELINKNO = sizeof(audioBuffer) / 2;
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dma.TCD->DLASTSGA = 0; // destination address offset
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dma.TCD->BITER_ELINKNO = sizeof(audioBuffer) / 2;
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; // enables interrupt when transfers half complete. SET TO 0 to disable DMA interrupts
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dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); // I2S1 register DMA writes to
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); // i2s channel that will trigger the DMA transfer when ready for data
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dma.enable();
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dma.attachInterrupt(isrDMA);
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#else
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attachInterruptVector(IRQ_SAI1, isrAudio);
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NVIC_ENABLE_IRQ(IRQ_SAI1);
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NVIC_SET_PRIORITY(IRQ_SAI1, 127);
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I2S1_TCSR |= 1<<8; // start generating TX FIFO interrupts
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#endif
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pinMode(13, OUTPUT);
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}
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bool add(int16_t* samples) {
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#ifdef USE_DMA
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if (freeBuffers == 0) {return false;}
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--freeBuffers;
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int16_t* dst = &audioBuffer[curBuffer * SAMPLES_PER_BUFFER];
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memcpy(dst, samples, SAMPLES_PER_BUFFER*sizeof(int16_t));
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arm_dcache_flush_delete(dst, SAMPLES_PER_BUFFER*sizeof(int16_t));
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curBuffer = (curBuffer + 1) % NUM_BUFFERS;
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return true;
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#else
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//return audioBuffer.add(samples);
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#endif
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}
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private:
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//uint16_t pos = 0;
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FASTRUN static void isrDMA() {
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dma.clearInterrupt();
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if (freeBuffers < NUM_BUFFERS) {++freeBuffers;}
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}
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/*
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// interrupt service routine
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FASTRUN static void isrAudio() {
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static constexpr volatile uint16_t* txReg = (uint16_t *)((uint32_t)&I2S1_TDR0 + 2);
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//static constexpr uint16_t* txReg = (uint16_t *)((uint32_t)&I2S1_TDR0 );
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if (CHANNELS == 2) {
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const int16_t sample1 = audioBuffer.getSample();
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*txReg = sample1;
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const int16_t sample2 = audioBuffer.getSample();
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*txReg = sample2;
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} else if (CHANNELS == 1) {
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const int16_t sample1 = audioBuffer.getSample();
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*txReg = sample1;
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*txReg = sample1;
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}
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//arm_dcache_flush_delete(txBuffer, txBufferSize);
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//digitalWriteFast(13, (pos / 2048) & 1);
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}
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*/
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private:
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FLASHMEM static void config_sai1() {
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CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
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double fs = SAMPLE_RATE_HZ;
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// PLL between 27*24 = 648MHz und 54*24=1296MHz
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int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
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int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
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double C = (fs * 256 * n1 * n2) / 24000000;
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int c0 = C;
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int c2 = 10000;
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int c1 = C * c2 - (c0 * c2);
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setAudioClock(c0, c1, c2, true);
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// clear SAI1_CLK register locations
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CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
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| CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
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//n1 = n1 / 2; //Double Speed for TDM
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CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
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| CCM_CS1CDR_SAI1_CLK_PRED(n1 - 1) // &0x07
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| CCM_CS1CDR_SAI1_CLK_PODF(n2 - 1); // &0x3f
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IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
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| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK
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// configure transmitter
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const int rsync = 0;
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const int tsync = 1;
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uint16_t by = 32; // ??
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// configure transmitter
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I2S1_TMR = 0;
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I2S1_TCR1 = I2S_TCR1_RFW(1);
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I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP | (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1)); // sync=0; tx is async;
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I2S1_TCR3 = I2S_TCR3_TCE;
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I2S1_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((by-1)) | I2S_TCR4_MF | I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP;
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I2S1_TCR5 = I2S_TCR5_WNW((by-1)) | I2S_TCR5_W0W((by-1)) | I2S_TCR5_FBT((by-1));
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I2S1_RMR = 0;
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I2S1_RCR1 = I2S_RCR1_RFW(1);
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I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP | (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1)); // sync=0; rx is async;
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I2S1_RCR3 = I2S_RCR3_RCE;
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I2S1_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((by-1)) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
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I2S1_RCR5 = I2S_RCR5_WNW((by-1)) | I2S_RCR5_W0W((by-1)) | I2S_RCR5_FBT((by-1));
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//CORE_PIN23_CONFIG = 3; // MCLK
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CORE_PIN21_CONFIG = 3; // RX_BCLK
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CORE_PIN20_CONFIG = 3; // RX_SYNC
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CORE_PIN7_CONFIG = 3; // TX_DATA0
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
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#ifdef USE_DMA
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I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
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#else
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I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE;
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#endif
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}
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FLASHMEM static void setAudioClock(int nfact, int32_t nmult, uint32_t ndiv, bool force) {// sets PLL4
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if (!force && (CCM_ANALOG_PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_ENABLE)) return;
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CCM_ANALOG_PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_BYPASS | CCM_ANALOG_PLL_AUDIO_ENABLE
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| CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2) // 2: 1/4; 1: 1/2; 0: 1/1
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| CCM_ANALOG_PLL_AUDIO_DIV_SELECT(nfact);
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CCM_ANALOG_PLL_AUDIO_NUM = nmult & CCM_ANALOG_PLL_AUDIO_NUM_MASK;
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CCM_ANALOG_PLL_AUDIO_DENOM = ndiv & CCM_ANALOG_PLL_AUDIO_DENOM_MASK;
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CCM_ANALOG_PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_POWERDOWN;//Switch on PLL
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while (!(CCM_ANALOG_PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK)) {}; //Wait for pll-lock
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const int div_post_pll = 1; // other values: 2,4
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CCM_ANALOG_MISC2 &= ~(CCM_ANALOG_MISC2_DIV_MSB | CCM_ANALOG_MISC2_DIV_LSB);
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if(div_post_pll>1) CCM_ANALOG_MISC2 |= CCM_ANALOG_MISC2_DIV_LSB;
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if(div_post_pll>3) CCM_ANALOG_MISC2 |= CCM_ANALOG_MISC2_DIV_MSB;
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CCM_ANALOG_PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS;//Disable Bypass
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}
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};
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