700 lines
18 KiB
C++
700 lines
18 KiB
C++
#ifndef MFRC522_H
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#define MFRC522_H
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#include "../../Debug.h"
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#include "../../io/SoftSPI.h"
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/**
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* RFID reader based on MFRC522
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* attached via SPI
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*
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* http://www.nxp.com/documents/data_sheet/MFRC522.pdf
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*
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* http://www.gorferay.com/initialization-and-anticollision-iso-iec-14433-3/
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* https://community.nxp.com/thread/437908
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* https://www.nxp.com/docs/en/application-note/AN10833.pdf
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* https://www.slideshare.net/contactsarbjeet/architecture-development-of-nfc-applications
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* http://www.gorferay.com/mifare-and-handling-of-uids/
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* http://www.proxmark.org/files/Documents/13.56%20MHz%20-%20MIFARE%20Classic/MIFARE%20Classic%20clones/ISSI_IS23SC4439_User_Manual.pdf
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*/
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class MFRC522 {
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public:
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static constexpr const char* NAME = "MFRC522";
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struct UID {
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uint8_t size = 0; // Number of bytes in the UID. 4, 7 or 10.
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uint8_t uidByte[10];
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uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
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};
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private:
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enum class Register {
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COMMAND_REG = 0x01 << 1,
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INTERRUPTS_REG = 0x02 << 1,
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COM_IRQ_REG = 0x04 << 1,
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DIV_IRQ_REG = 0x05 << 1,
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ERROR_REG = 0x06 << 1,
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STATUS1_REG = 0x07 << 1,
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STATUS2_REG = 0x08 << 1,
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FIFO_DATA_REG = 0x09 << 1, // access fifo buffer
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FIFO_LEVEL_REG = 0x0A << 1, // number of available fifo data
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CONTROL_REG = 0x0C << 1,
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BIT_FRAMING_REG = 0x0D << 1,
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COLL_REG = 0x0E << 1,
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MODE_REG = 0x11 << 1,
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TX_MODE_REG = 0x12 << 1,
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RX_MODE_REG = 0x13 << 1,
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TX_CONTROL_REG = 0x14 << 1,
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TX_AUTO_REG = 0x15 << 1,
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DEMOG_REG = 0x19 << 1,
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CRC_RES_H = 0x21 << 1,
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CRC_RES_L = 0x22 << 1,
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MOD_WIDTH_REG = 0x24 << 1,
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T_MODE_REG = 0x2A << 1,
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T_PRESCALER_REG = 0x2B << 1,
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T_RELOAD_REG_H = 0x2C << 1,
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T_RELOAD_REG_L = 0x2D << 1,
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TEST_SEL_1_REG = 0x31 << 1,
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TEST_SEL_2_REG = 0x32 << 1,
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VERSION_REG = 0x37 << 1, // software version
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};
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enum class Command {
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IDLE = 0x00,
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MEM = 0x01,
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GEN_RANDOM_ID = 0x02,
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CALC_CRC = 0x03,
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TRANSMIT = 0x04,
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NO_CMD_CHANGE = 0x07,
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RECEIVE = 0x08,
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TRANSCEIVE = 0x0C,
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MF_AUTHENT = 0x0E,
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SOFT_RESET = 0x0F,
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};
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enum class PICCComand {
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REQA = 0x26,
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PICC_CMD_READ = 0x30,
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PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
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PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
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PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
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PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 2
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PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 3
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PICC_CMD_HLTA = 0x50, // HaLT command, Typ
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};
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enum class Status {
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OK,
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TIMEOUT_IRQ,
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TIMEOUT_MANUAL,
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TIMEOUT_CRC,
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ERROR,
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RESPONSE_TOO_LONG,
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COLLISION,
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INVALID,
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INVALID_ATQA,
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INTERNAL_ERROR,
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WRONG_CRC,
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WRONG_BCC,
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};
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/** convert status-code to status string */
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const char* getStatusStr(const Status s) const;
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struct CommandReg {
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uint8_t command : 4;
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uint8_t power_down : 1;
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uint8_t receiver_off : 1;
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uint8_t reserved : 2;
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};
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struct InterruptsReg {
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uint8_t timerInterruptEnable : 1;
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uint8_t errorInterruptEnable : 1;
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uint8_t loAlertInterruptEnable : 1;
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uint8_t hiAlertInterruptEnable : 1;
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uint8_t idleInterruptEnable : 1;
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uint8_t rxInterruptEnable : 1;
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uint8_t txInterruptEnable : 1;
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uint8_t inverted : 1;
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};
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private:
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public:
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/** init */
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void init();
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/** check whether a RFID-reader is present or not */
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bool isAvailable();
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/** is there a card present? */
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bool isCard();
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/** yes, card is present -> read it */
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bool select(UID* uidOut);
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/** read the given 14-byte sector from the card */
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void read(uint8_t address);
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/** stop talking to the card */
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void halt();
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/** perform selftest */
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void selftest();
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private:
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void stopCrypto1() {
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clearRegBits(Register::STATUS2_REG, 0x08); // reset MFCrypto1On
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}
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void antennaOn();
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Status requestA(uint8_t* bufferATQA, uint8_t* bufferSize) {
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return piccREQAorWUPA(PICCComand::REQA, bufferATQA, bufferSize);
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}
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Status piccREQAorWUPA(const PICCComand cmd, uint8_t* buffer, uint8_t* bufferSize);
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/** get card-type-name for the given 2-byte ATQA response */
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const char* getCardType(const uint8_t* atqa) const;
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Status anticol(int level, UID* uid);
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Status select(int level, uint8_t* uidPart, UID* uid);
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/**
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* calculate the CRC for the given bytes and write them (2 bytes) to the given destination
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* NOTE: the CRC depends on the settings of ModeReg (bit 0 and 1) which control
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* the CRC-16's preset: 0x0000 0x6363 0xa671 0xffff
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* 0x6363 seems to be the "correct" one?!
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*/
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Status calculateCRC(const uint8_t *data, const uint8_t length, uint8_t* result);
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Status transceive(const uint8_t* srcData, const uint8_t srcDataLen, uint8_t* dstData, uint8_t* dstDataLen, uint8_t* validBits = nullptr, uint8_t rxAlign = 0, bool checkCRC = false) {
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debugMod1(NAME, "transceive %d bytes", srcDataLen);
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debugShow(srcData, srcDataLen);
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const Status s = picc(Command::TRANSCEIVE, 0x30, srcData, srcDataLen, dstData, dstDataLen, validBits, rxAlign, checkCRC);
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debugMod2(NAME, "transceive: %s, returned %d bytes", getStatusStr(s), *dstDataLen);
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debugShow(dstData, *dstDataLen);
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return s;
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}
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void fillFIFO(const uint8_t* srcData, const uint8_t srcDataLen) {
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setRegBits(Register::FIFO_LEVEL_REG, 0x80); // flush FIFO (empty any existing data)
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if (readReg8(Register::FIFO_LEVEL_REG) != 0) {
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debugMod(NAME, "!!!!!!!!!!!!!!!!! FIFO NOT EMPTY THOUGH IT SHOULD BE!\n");
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}
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writeReg(Register::FIFO_DATA_REG, srcData, srcDataLen); // write to-be-sent data to FIFO
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if (readReg8(Register::FIFO_LEVEL_REG) != srcDataLen) {
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debugMod(NAME, "!!!!!!!!!!!!!!!!!failed to fill fifo\n");
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}
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}
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void ensureSane() {
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setRegBits(Register::FIFO_LEVEL_REG, 0x80); // flush FIFO (empty any existing data)
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//writeReg8(Register::FIFO_LEVEL_REG, 0x80); // flush FIFO (empty any existing data)
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writeReg8(Register::COMMAND_REG, (int) Command::IDLE); // stop previous commands
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}
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Status picc(Command cmd, const uint8_t waitIRQ, const uint8_t* srcData, const uint16_t srcDataLen, uint8_t* dstData, uint8_t* dstLen, uint8_t* validBits, uint8_t rxAlign, bool checkCRC);
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private:
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void writeReg8(const Register reg, const Command cmd) {
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writeReg8(reg, (uint8_t) cmd);
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}
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void writeReg8(const Register reg, const uint8_t value) {
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spi::chipSelect();
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writeTo((int)reg);
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spi::writeByte(value);
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spi::chipDeselect();
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}
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void setRegBits(const Register reg, const uint8_t mask) {
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const uint8_t tmp = readReg8(reg);
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writeReg8(reg, tmp | mask);
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}
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void clearRegBits(const Register reg, const uint8_t mask) {
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const uint8_t tmp = readReg8(reg);
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writeReg8(reg, tmp & (~mask));
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}
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void writeReg(const Register reg, const uint8_t* data, const uint16_t len) {
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spi::chipSelect();
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writeTo((int)reg);
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for (int i = 0; i < len; ++i){
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spi::writeByte(data[i]);
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}
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spi::chipDeselect();
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}
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uint8_t readReg8(const Register reg) {
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spi::chipSelect();
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readFrom((int)reg);
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const uint8_t res = spi::readByte();
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spi::chipDeselect();
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return res;
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}
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/** read multiple bytes from the same register (mainly FIFO) */
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void readReg(const Register reg, uint8_t* dst, const uint8_t count, const uint8_t rxAlign = 0);
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// highest bit denotes whether reading or writing
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void readFrom(uint8_t address) {
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spi::writeByte(address | 0x80);
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}
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void writeTo(uint8_t address) {
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spi::writeByte(address);
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}
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};
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void ICACHE_FLASH_ATTR MFRC522::init() {
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debugMod(NAME, "init");
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spi::init();
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//os_delay_us(5000);
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// Reset baud rates
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writeReg8(Register::TX_MODE_REG, 0x00);
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writeReg8(Register::RX_MODE_REG, 0x00);
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// Reset ModWidthReg
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writeReg8(Register::MOD_WIDTH_REG, 0x26);
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writeReg8(Register::T_MODE_REG, 0x80);
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writeReg8(Register::T_PRESCALER_REG, 0xA9);
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writeReg8(Register::T_RELOAD_REG_L, 0xE8);
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writeReg8(Register::T_RELOAD_REG_H, 0x03);
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writeReg8(Register::TX_AUTO_REG, 0x40);
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writeReg8(Register::MODE_REG, 0x3D); // very important. set CRC preset to 0x6363 by setting bit 0 and clearing bit 1 in MODE_REG
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antennaOn();
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writeReg8(Register::COMMAND_REG, Command::IDLE);
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}
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void ICACHE_FLASH_ATTR MFRC522::readReg(const Register reg, uint8_t* dst, const uint8_t count, const uint8_t rxAlign) {
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spi::chipSelect();
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// address for reading (MSB = 1)
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const uint8_t address = (int) reg | 0x80;
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spi::writeByte(address);
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int i;
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for (i = 0; i < count-1; ++i) {
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if ( (i == 0) && rxAlign ) {
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uint8_t mask = (0xFF << rxAlign) & 0xFF;
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const uint8_t value = spi::readWriteByte(address);
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dst[0] = (dst[0] & ~mask) | (value & mask);
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} else {
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dst[i] = spi::readWriteByte(address);
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}
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}
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// read last byte and stop reading
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dst[i] = spi::readWriteByte(0);
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spi::chipDeselect();
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}
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MFRC522::Status ICACHE_FLASH_ATTR MFRC522::picc(Command cmd, const uint8_t waitIRQ, const uint8_t* srcData, const uint16_t srcDataLen, uint8_t* dstData, uint8_t* dstLen, uint8_t* validBits, uint8_t rxAlign, bool checkCRC) {
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const uint8_t txLastBits = validBits ? *validBits : 0;
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const uint8_t bitFraming = (rxAlign << 4) + txLastBits;
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//os_printf("-- txLastBits: %d, bitFraming: %d \n", txLastBits, bitFraming);
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ensureSane();
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writeReg8(Register::COM_IRQ_REG, 0x7f); // clear interrupt flags
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fillFIFO(srcData, srcDataLen);
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writeReg8(Register::BIT_FRAMING_REG, bitFraming);
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writeReg8(Register::COMMAND_REG, (int) cmd);
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if (cmd == Command::TRANSCEIVE) {
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//os_printf("-- start seding...\n");
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setRegBits(Register::BIT_FRAMING_REG, 0x80); // startSend = 1
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}
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//const uint8_t _errReg = readReg8(Register::ERROR_REG);
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//os_printf("cur err reg: %d\n", (int)_errReg);
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int maxRuns = 10;
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while(true) {
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const uint8_t res = readReg8(Register::COM_IRQ_REG);
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//os_printf("irq reg: %d\n", res);
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// received the interrupt we are waiting for?
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if (res & waitIRQ) {
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//debugMod(NAME, "got needed interrupt -> done");
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//os_printf("got needed interrupt\n");
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break;
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}
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if (res & 0x01) {
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return Status::TIMEOUT_IRQ;
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}
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if (--maxRuns == 0) {
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//debugMod(NAME, "TIMEOUT");
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//os_printf("picc() Timeout\n");
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return Status::TIMEOUT_MANUAL;
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}
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os_delay_us(1000*5);
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}
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// buffer overflow?
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const uint8_t errReg = readReg8(Register::ERROR_REG);
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if (errReg & 0x13) {return Status::ERROR;}
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// caller wants to read a response?
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if (dstData && dstLen) {
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const uint8_t n = readReg8(Register::FIFO_LEVEL_REG);
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debugMod1(NAME, "got %d bytes to read", (int)n);
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//os_printf("got %d bytes to read\n", (int) n);
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// not enough space for the response data?
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if (n > *dstLen) { return Status::RESPONSE_TOO_LONG; }
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// read response
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*dstLen = n;
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readReg(Register::FIFO_DATA_REG, dstData, n, rxAlign);
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uint8_t _validBits = readReg8(Register::CONTROL_REG) & 0x07;
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if (validBits) {
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*validBits = _validBits;
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}
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#ifdef WITH_DEBUG
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// ensure fifo is now empty
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if (readReg8(Register::FIFO_LEVEL_REG) != 0) {
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debugMod(NAME, "!! FIFO is not empty though it should be!");
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return Status::INTERNAL_ERROR;
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}
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#endif
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}
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if (errReg & 0x08) {
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return Status::COLLISION;
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}
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// TODO CRC
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return Status::OK;
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}
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MFRC522::Status ICACHE_FLASH_ATTR MFRC522::calculateCRC(const uint8_t *data, const uint8_t length, uint8_t* result) {
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debugMod1(NAME, "calculate CRC for %d bytes", length);
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writeReg8(Register::COMMAND_REG, Command::IDLE); // Stop any active command.
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writeReg8(Register::DIV_IRQ_REG, 0x04); // Clear the CRCIRq interrupt request bit
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fillFIFO(data, length); // fill the FIFO with the data to CRC
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writeReg8(Register::COMMAND_REG, Command::CALC_CRC); // Start the calculation
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// Wait for the CRC calculation to complete
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for (int i = 0; i < 25; ++i) {
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os_delay_us(1000*1);
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// wait for CRCIRq to be set
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const uint8_t n = readReg8(Register::DIV_IRQ_REG);
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// CRCIRq bit set - calculation done
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if (n & 0x04) {
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writeReg8(Register::COMMAND_REG, Command::IDLE); // Stop calculating CRC for new content in the FIFO.
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result[0] = readReg8(Register::CRC_RES_L);
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result[1] = readReg8(Register::CRC_RES_H);
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return Status::OK;
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}
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}
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debugMod(NAME, "CRC TIMEOUT");
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return Status::TIMEOUT_CRC;
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}
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const char* ICACHE_FLASH_ATTR MFRC522::getCardType(const uint8_t* atqa) const {
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const uint16_t resp = atqa[0] << 8 | atqa[1];
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if (resp == 0x0400) {return "MFOne-S50";} // http://www.elechouse.com/elechouse/images/product/13.56MHZ_RFID_Module/mifare_S50.pdf
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if (resp == 0x0200) {return "MFOne-S70";}
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if (resp == 0x4400) {return "MF-UltraLight";}
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if (resp == 0x0800) {return "MF-Pro";}
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if (resp == 0x4403) {return "MF Desire";}
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return "Unknown";
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}
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MFRC522::Status ICACHE_FLASH_ATTR MFRC522::anticol(int level, UID* uid) {
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debugMod1(NAME, "anticol(%d)", level);
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// Prepare MFRC522
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clearRegBits(Register::COLL_REG, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
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uint8_t out[9];
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uint8_t res[9];
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uint8_t resLen;
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Status s;
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// send 2 bytes: 0x93 0x20 and expect 5 bytes of response : 4 bytes UID + 1 byte BCC checksum
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// the first byte of the UID might be 0x88 to indicate that there are more requests needed
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// to get the full UID
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resLen = 5;
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out[0] = (uint8_t)PICCComand::PICC_CMD_SEL_CL1;
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out[1] = 0x20;
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writeReg8(Register::BIT_FRAMING_REG, 0);
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s = transceive(out, 2, res, &resLen);
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// transceive failed?
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if (s != Status::OK) {return s;}
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// response is SN0 SN1 SN2 SN3 BCC where BCC = SN0^SN1^SN2^SN3 -> check this!
|
|
const uint8_t bcc = res[0] ^ res[1] ^ res[2] ^ res[3];
|
|
debugMod2(NAME, "check BCC: %02x == %02x ?", bcc, res[4]);
|
|
|
|
// NOTES
|
|
// if the received UID starts with SN0 = 0x88, then we have to read the next block (like UTF-8)
|
|
// if the received UID starts with SN0 = 0x08, it is a random number that will change every time
|
|
|
|
// adjust the UID-result accordingly
|
|
if (res[0] != 0x88) {uid->uidByte[uid->size] = res[0]; ++uid->size;}
|
|
{uid->uidByte[uid->size] = res[1]; ++uid->size;}
|
|
{uid->uidByte[uid->size] = res[2]; ++uid->size;}
|
|
{uid->uidByte[uid->size] = res[3]; ++uid->size;}
|
|
|
|
// go on with select
|
|
return select(level, res, uid);
|
|
|
|
}
|
|
|
|
MFRC522::Status ICACHE_FLASH_ATTR MFRC522::select(int level, uint8_t* uidPart, UID* uid) {
|
|
|
|
debugMod1(NAME, "select(%d)", level);
|
|
|
|
uint8_t cmd = (uint8_t) PICCComand::PICC_CMD_SEL_CL1; // TODO: depends on level
|
|
|
|
uint8_t bcc = uidPart[0] ^ uidPart[1] ^ uidPart[2] ^ uidPart[3];
|
|
uint8_t out[9] = {cmd, 0x70, uidPart[0], uidPart[1], uidPart[2], uidPart[3], bcc, 0x00, 0x00};
|
|
|
|
// replace 0x00 0x00 with the crc
|
|
calculateCRC(out, 7, &out[7]);
|
|
|
|
// transmit
|
|
uint8_t res[3];
|
|
uint8_t resLen = 3;
|
|
Status status = transceive(out, 9, res, &resLen);
|
|
|
|
// NOTES on SAK (selective ACK)
|
|
// result starts with 0x04? -> UID not complete, go on reading!
|
|
// result starts with 0x08? -> UID complete,
|
|
// this one also contains some details on the card we see
|
|
uint8_t SAK = res[0];
|
|
|
|
// another UID part needs to be read? (max: 3)
|
|
if (SAK == 0x04) { return anticol(level+1, uid); }
|
|
|
|
// done
|
|
return status;
|
|
|
|
}
|
|
|
|
/** is there a card present? */
|
|
bool ICACHE_FLASH_ATTR MFRC522::isCard() {
|
|
|
|
debugMod(NAME, "isCard()");
|
|
|
|
uint8_t bufferATQA[2] = {0x00, 0x00};
|
|
uint8_t bufferSize = sizeof(bufferATQA);
|
|
|
|
// Reset baud rates
|
|
writeReg8(Register::TX_MODE_REG, 0x00);
|
|
writeReg8(Register::RX_MODE_REG, 0x00);
|
|
|
|
// Reset ModWidthReg
|
|
writeReg8(Register::MOD_WIDTH_REG, 0x26);
|
|
|
|
// send REQA
|
|
Status res = requestA(bufferATQA, &bufferSize);
|
|
debugMod1(NAME, "isCard: %s", getStatusStr(res));
|
|
|
|
// card-type?
|
|
if (res == Status::OK) {
|
|
debugMod1(NAME, "card type: %s", getCardType(bufferATQA));
|
|
}
|
|
|
|
// done
|
|
return res == Status::OK;
|
|
|
|
}
|
|
|
|
/** yes, card is present -> read it */
|
|
bool ICACHE_FLASH_ATTR MFRC522::select(UID* uidOut) {
|
|
|
|
debugMod(NAME, "select()");
|
|
|
|
ensureSane();
|
|
|
|
// reset UID
|
|
uidOut->size = 0;
|
|
|
|
Status res;
|
|
res = anticol(1, uidOut);
|
|
debugShow(uidOut->uidByte, 10);
|
|
|
|
return (res == Status::OK);
|
|
|
|
}
|
|
|
|
/** read the given 14-byte sector from the card */
|
|
void ICACHE_FLASH_ATTR MFRC522::read(uint8_t address) {
|
|
|
|
debugMod1(NAME, "read(%d)", address);
|
|
|
|
os_delay_us(1000*50);
|
|
|
|
clearRegBits(Register::COLL_REG, 0x80);
|
|
writeReg8(Register::BIT_FRAMING_REG, 0);
|
|
|
|
// READ command: 0x30 ADR CRC1 CRC2
|
|
uint8_t buffer[4] = {(uint8_t)PICCComand::PICC_CMD_READ, address};
|
|
|
|
// calculate the CRC
|
|
calculateCRC(buffer, 2, &buffer[2]);
|
|
|
|
// response-buffer
|
|
uint8_t res[16];
|
|
uint8_t resLen = 16;
|
|
|
|
// send
|
|
transceive(buffer, 4, res, &resLen);
|
|
|
|
}
|
|
|
|
/** stop talking to the card */
|
|
void ICACHE_FLASH_ATTR MFRC522::halt() {
|
|
|
|
debugMod(NAME, "halt()");
|
|
|
|
// HALT command: 0x50 ADR CRC1 CRC2
|
|
uint8_t buffer[4] = {(uint8_t)PICCComand::PICC_CMD_HLTA, 0x00};
|
|
|
|
// calculate the CRC
|
|
calculateCRC(buffer, 2, &buffer[2]);
|
|
|
|
// send
|
|
uint8_t resLen = 1;
|
|
transceive(buffer, 4, buffer, &resLen);
|
|
|
|
}
|
|
|
|
void ICACHE_FLASH_ATTR MFRC522::selftest() {
|
|
|
|
//os_printf("MODE_REG: %d\n", readReg8(Register::MODE_REG));
|
|
//writeReg8(Register::MODE_REG, 61);
|
|
//os_printf("MODE_REG: %d\n", readReg8(Register::MODE_REG));
|
|
|
|
uint8_t res[2];
|
|
|
|
// MUST BE 3c a2
|
|
uint8_t out2[9] = {0x93, 0x70, 0x12, 0x34, 0x56, 0x78, 0x08, 0x00, 0x00};
|
|
calculateCRC(out2, 7, res);
|
|
debugShow(res, 2);
|
|
|
|
}
|
|
|
|
bool ICACHE_FLASH_ATTR MFRC522::isAvailable() {
|
|
return readReg8(Register::MODE_REG) == 0x3D;
|
|
}
|
|
|
|
MFRC522::Status ICACHE_FLASH_ATTR MFRC522::piccREQAorWUPA(const PICCComand cmd, uint8_t* buffer, uint8_t* bufferSize) {
|
|
|
|
clearRegBits(Register::COLL_REG, 0x80);
|
|
uint8_t validBits = 7;
|
|
const uint8_t _cmd = (uint8_t) cmd;
|
|
|
|
const Status status = transceive(&_cmd, 1, buffer, bufferSize, &validBits);
|
|
|
|
if (status != Status::OK) {return status;}
|
|
|
|
//os_printf("response-size: %d, valid bits: %d\n", (int)*bufferSize, (int)validBits);
|
|
|
|
// ATQA must be 16 bits
|
|
if ((*bufferSize != 2) || (validBits != 0)) {
|
|
return Status::INVALID_ATQA;
|
|
}
|
|
|
|
return Status::OK;
|
|
|
|
}
|
|
|
|
/** convert status-code to status string */
|
|
const char* ICACHE_FLASH_ATTR MFRC522::getStatusStr(const Status s) const {
|
|
switch(s) {
|
|
case Status::OK: return "OK";
|
|
case Status::TIMEOUT_IRQ: return "TIMEOUT (IRQ)";
|
|
case Status::TIMEOUT_MANUAL: return "TIMEOUT (manual)";
|
|
case Status::TIMEOUT_CRC: return "TIMEOUT (crc)";
|
|
case Status::ERROR: return "ERROR";
|
|
case Status::RESPONSE_TOO_LONG: return "RESPONSE TOO LONG";
|
|
case Status::COLLISION: return "COLLISION";
|
|
case Status::INVALID: return "INVALID";
|
|
case Status::INVALID_ATQA: return "INVALID_ATQA";
|
|
case Status::INTERNAL_ERROR: return "INTERNAL_ERROR";
|
|
case Status::WRONG_CRC: return "WRONG_CRC";
|
|
case Status::WRONG_BCC: return "WRONG_BCC";
|
|
default: return "UNKNOWN STATUS";
|
|
}
|
|
}
|
|
|
|
void ICACHE_FLASH_ATTR MFRC522::antennaOn() {
|
|
uint8_t val = readReg8(Register::TX_CONTROL_REG);
|
|
if ((val & 0x03) != 0x03) {
|
|
writeReg8(Register::TX_CONTROL_REG, val | 0x03);
|
|
}
|
|
val = readReg8(Register::TX_CONTROL_REG);
|
|
}
|
|
|
|
#endif // MFRC522_H
|