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some lora changes

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This commit is contained in:
FrankE
2020-07-04 13:45:05 +02:00
parent b188ef50b9
commit 0e5de320c7
1 changed files with 62 additions and 37 deletions
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99
ext/rf/SX1276.h
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@@ -130,8 +130,10 @@ template <typename SPI, int PIN_SLAVE_SEL, int PIN_RESET, int PIN_DIO0> class SX
public:
struct PacketDetails {
int16_t rssi; // can be smaller than -128!
float snr;
int8_t rssi; // can be smaller than -128! -> use getter method (-128 - 1 -> + 127)
int8_t snr4; // SNR*4 (must be scaled by 0.25)
float getSNR() const {return snr4 * 0.25f;}
int16_t getRSSI() const {return (rssi<0) ? (rssi) : (-256 + rssi);}
};
public:
@@ -325,16 +327,17 @@ public:
/** switch to idle mode */
void idle() {
debugMod(NAME, "idle()");
//debugMod(NAME, "idle()");
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STDBY);
}
/** switch to sleep mode */
void sleep() {
debugMod(NAME, "sleep()");
//debugMod(NAME, "sleep()");
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
}
/** is the device currently transmitting? */
bool isTransmitting() {
if ((readRegister(REG_OP_MODE) & MODE_TX) == MODE_TX) {return true;}
if (readRegister(REG_IRQ_FLAGS) & IRQ_TX_DONE_MASK) {writeRegister(REG_IRQ_FLAGS, IRQ_TX_DONE_MASK);} // clear TX-done IRQ flag
@@ -344,7 +347,7 @@ public:
/** send the given data */
int send(const uint8_t* data, uint8_t len, bool async) {
debugMod1(NAME, "send(%d bytes)", len);
debugMod2(NAME, "tx(%d bytes, async:%d)", len, async);
//if (len > MAX_PKT_LENGTH) {return -1;}
if (isTransmitting()) {return 0;}
@@ -352,18 +355,14 @@ public:
// put in standby mode
idle();
//if (implicitHeader) {
// implicitHeaderMode();
//} else {
explicitHeaderMode();
//}
explicitHeaderMode();
// reset FIFO address and payload length
writeRegister(REG_FIFO_ADDR_PTR, 0);
writeRegister(REG_PAYLOAD_LENGTH, 0);
// write data into FIFO
debugMod(NAME, "writing FIFO");
//debugMod(NAME, "writing FIFO");
for (uint16_t i = 0; i < len; ++i) {writeRegister(REG_FIFO, data[i]);}
writeRegister(REG_PAYLOAD_LENGTH, len);
@@ -371,38 +370,43 @@ public:
//if ((async) && (_onTxDone)) writeRegister(REG_DIO_MAPPING_1, 0x40); // DIO0 => TXDONE
// put in TX mode
debugMod(NAME, "starting TX");
//debugMod(NAME, "starting TX");
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
if (!async) {
debugMod(NAME, "waiting");
//debugMod(NAME, "waiting");
while ((readRegister(REG_IRQ_FLAGS) & IRQ_TX_DONE_MASK) == 0) {yield();} // wait for TX done
writeRegister(REG_IRQ_FLAGS, IRQ_TX_DONE_MASK); // clear IRQ TX-done flag
debugMod(NAME, "done");
debugMod(NAME, "tx done");
}
return len;
}
/** switch to RX-mode. either for a single frame or permanent */
void setRX(bool single) {
// reset FIFO address
writeRegister(REG_FIFO_ADDR_PTR, 0);
// put in single RX mode
if (single) {
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
} else {
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
}
/** blocking wait for TX to finish */
void waitTxComplete() {
}
/** switch to RX mode, but only for a single packet */
void rxSingle() {
enableRX(true);
}
/** switch to RX mode, continuously */
void rxContinuous() {
enableRX(false);
}
/** fetch one received packet, if any is available. requires setRX(..) beforehand to actually receive something! */
/**
* fetch one received packet, if any is available.
* requires rxSingle()/rxContinuous() beforehand to actually receive something!!!
*/
int read(uint8_t* dst, PacketDetails* det) {
uint8_t irqFlags = readRegister(REG_IRQ_FLAGS);
@@ -428,8 +432,8 @@ public:
// read the details?
if (det) {
det->rssi = (readRegister(REG_PKT_RSSI_VALUE) - (curFreq < 868E6 ? 164 : 157));
det->snr = ((int8_t)readRegister(REG_PKT_SNR_VALUE)) * 0.25f;
det->rssi = (readRegister(REG_PKT_RSSI_VALUE) - (curFreq < 868E6 ? 164 : 157)); // can be smaller than -128 !! -> overflow -> use getter method
det->snr4 = ((int8_t)readRegister(REG_PKT_SNR_VALUE)); // SNR*4 (must be scaled by 0.25) -> use getter method
}
// put in standby mode
@@ -455,19 +459,40 @@ private:
usleep(5000);
}
/**
* configure explicit header mode.
* TX: the SX1276 appends an automatically created header in front of every packet
* RX: the SX1276 expects and automatically reads the header in front of every received packet
* Note: the header contains the packet's length, and the FEC (codingRate) for the content
* the header itself always has a coding rate of 8/4(?)
*/
void explicitHeaderMode() {
writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) & 0xfe);
}
void implicitHeaderMode() {
writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) | 0x01);
// void implicitHeaderMode() {
// writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) | 0x01);
// }
/** switch to RX-mode. either for a single frame or permanent */
void enableRX(bool single) {
debugMod1(NAME, "rx(single: %d)", single);
// reset FIFO address
writeRegister(REG_FIFO_ADDR_PTR, 0);
// put in single RX mode
if (single) {
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
} else {
writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
}
}
// uint8_t getMode() {
// const uint8_t mode = readRegister(REG_OP_MODE);
// debugMod1(NAME, "mode: %d", mode);
// return mode;
// }
/** set the RF frequency to use (in Hz) */
void setFrequency(uint32_t hz) {